EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 159

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
Operating Modes
•
•
Clock Synchronization for Handshake
The Clock synchronizing mechanism can function as a handshake, enabling receivers to
cope with fast data transfers, on either a byte or bit level. The byte level allows a device to
receive a byte of data at a fast rate, but allows the device more time to store the received
byte or to prepare another byte for transmission. Slaves hold the SCL line Low after recep-
tion and acknowledge the byte, forcing the master into a wait state until the slave is ready
for the next byte transfer in a handshake procedure.
Master Transmit
In MASTER TRANSMIT mode, the I
Enter MASTER TRANSMIT mode by setting the STA bit in the I2C_CTL register to 1.
The I
When a START condition is transmitted, the IFLG bit is 1 and the status code in the
I2C_SR register is
loaded with either a 7-bit slave address or the first part of a 10-bit slave address, with the
lsb cleared to 0 to specify TRANSMIT mode. The IFLG bit should now be cleared to 0 to
prompt the transfer to continue.
After the 7-bit slave address (or the first part of a 10-bit address) plus the Write bit are
transmitted, the IFLG is set again. A number of status codes are possible in the I2C_SR
register. See I
A STOP condition and a data bit
A repeated START condition and a STOP condition
2
C then tests the I
2
C Master Transmit Status Codes.
08h
2
. Before this interrupt is serviced, the I2C_DR register must be
C bus and transmits a START condition when the bus is free.
P R E L I M I N A R Y
2
C transmits a number of bytes to a slave receiver.
Product Specification
I2C Serial I/O Interface
eZ80F92/eZ80F93
147