EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 124

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
BRG Control Registers
Note:
•
•
UART Baud Rate Generator Register—Low and High Bytes
The registers hold the Low and High bytes of the 16-bit divisor count loaded by the pro-
cessor for UART baud rate generation. The 16-bit clock divisor value is returned by
{UARTx_BRG_H, UARTx_BRG_L}, where x is either 0 or 1 to identify the two available
UART devices. Upon RESET, the 16-bit BRG divisor value resets to
16-bit divisor value must be between
are invalid, and proper operation is not guaranteed. As a result, the minimum BRG clock
divisor ratio is 2.
A Write to either the Low- or High-byte registers for the BRG Divisor Latch causes both
bytes to be loaded into the BRG counter. The count is then restarted.
Bit 7 of the associated UART Line Control register (UARTx_LCTL) must be set to 1 to
access this register. See Tables 53 and 54. Refer to the UART Line Control Register
(UARTx_LCTL) on page 118 for more information.
Table 53. UART Baud Rate Generator Register—Low Bytes
(UART0_BRG_L = 00C0h, UART1_BRG_L = 00D0h)
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
[7:0]
UART_BRG_L
Program the UARTx_BRG_L and UARTx_BRG_H registers
Clear UARTx_LCTL[7] to 0 to disable access of the BRG divisor registers
The UARTx_BRG_L registers share the same address space with the
UARTx_RBR and UARTx_THR registers. The UARTx_BRG_H registers share
the same address space with the UARTx_IER registers. Bit 7 of the associated
UART Line Control register (UARTx_LCTL) must be set to 1 to enable access to
the BRG registers.
Value
00h–
FFh
R/W
Description
These bits represent the Low byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value is
returned by {UART_BRG_H, UART_BRG_L}.
P R E L I M I N A R Y
7
0
R/W
6
0
0002h
R/W
5
0
and
Universal Asynchronous Receiver/Transmitter
FFFFh
R/W
4
0
as the values
R/W
3
0
Product Specification
R/W
2
0
0002h
eZ80F92/eZ80F93
0000h
R/W
. The initial
1
1
and
0001h
R/W
0
0
112