EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 77

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

Table 20. Motorola Bus Mode Read States
PS015308-0404
STATE S0
STATE S1
STATE S2
STATE S3
Motorola Bus Mode
The Read cycle starts in state S0. The CPU drives R/W High to identify a Read cycle.
Entering state S1, the CPU drives a valid address on the address bus, ADDR[23:0].
On the rising edge of state S2, the CPU asserts AS and DS.
During state S3, no bus signals are altered.
Chip selects configured for Motorola bus mode modify the CPU bus signals to duplicate
an eight-state memory transfer similar to that found on Motorola-style microcontrollers.
The bus signals (and eZ80F92 I/O pins) are mapped as illustrated in Figure 16.
Figure 16.Motorola Bus Mode Signal and Pin Mapping
During Write operations, the Motorola bus mode employs 8 states (S0, S1, S2, S3, S4, S5,
S6, and S7) as described in Motorola Bus Mode Read States.
eZ80 Bus Mode
Signals (Pins)
ADDR[23:0]
DATA[7:0]
INSTRD
MREQ
IORQ
WAIT
WR
RD
P R E L I M I N A R Y
Bus Mode
Controller
Motorola Bus
Signal Equvalents
AS
DS
R/W
DTACK
MREQ
IORQ
ADDR[23:0]
DATA[7:0]
Chip Selects and Wait States
Product Specification
eZ80F92/eZ80F93
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