EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 119

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

UART Functional Description
PS015308-0404
UART Functions
The UART function implements:
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The UART function implements:
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UART Transmitter
The transmitter block controls the data transmitted on the TxD output. It implements the
FIFO, accessed through the UARTx_THR register, the transmit shift register, the parity
generator, and control logic for the transmitter to control parameters for the asynchronous
communication protocol.
The UARTx_THR is a Write Only register. The processor writes the data byte to be trans-
mitted into this register. In the FIFO mode, up to 16 data bytes can be written via the
UARTx_THR register. The data byte from the FIFO is transferred to the transmit shift reg-
ister at the appropriate time and transmitted out on TxD output. After SYNC_RESET, the
UARTx_THR register is empty. Therefore, the Transmit Holding Register Empty (THRE)
bit (bit 5 of the UARTx_LSR register) is 1 and an interrupt is sent to the processor (if
interrupts are enabled). The processor can reset this interrupt by loading data into the
UARTx_THR register, which clears the transmitter interrupt.
The transmit shift register places the byte to be transmitted on the TxD signal serially. The
least-significant bit of the byte to be transmitted is shifted out first and the most-significant
bit is shifted out last. The control logic within the block adds the asynchronous communi-
cation protocol bits to the data byte being transmitted. The transmitter block obtains the
parameters for the protocol from the bits programmed via the UARTx_LCTL register.
When enabled, an interrupt is generated after the most recent protocol bit is transmitted,
which the processor may reset by loading data into the UARTx_THR register. The TxD
output is set to 1 if the transmitter is idle (it does not contain any data to be transmitted).
The transmitter operates with the Baud Rate Generator (BRG) clock. The data bits are
placed on the TxD output one time every 16 BRG clock cycles. The transmitter block also
implements a parity generator that attaches the parity bit to the byte, if programmed. For
The transmitter and associated control logic
The receiver and associated control logic
The modem interface and associated logic
The transmitter and associated control logic
The receiver and associated control logic
The modem interface and associated logic
P R E L I M I N A R Y
Universal Asynchronous Receiver/Transmitter
Product Specification
eZ80F92/eZ80F93
107