EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 207

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
RAM Control Registers
RAM Control Register
The internal data RAM can be disabled by clearing the RAM_EN bit. The default, upon
RESET, is for RAM to be enabled.
Table 112. RAM Control Register (RAM_CTL = 00B4h)
RAM Address Upper Byte Register
The RAM_ADDR_U register defines the upper byte of the address for the on-chip RAM.
If enabled, RAM addresses assume priority over all Chip Selects. The external Chip Select
signals are not asserted if the corresponding RAM address is enabled.
Table 113. RAM Address Upper Byte Register (RAM_ADDR_U = 00B5h)
Bit
Reset
CPU Access
Note: R/W = Read/Write; R = Read Only.
Bit
Position
7
RAM_EN
[6:0]
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
RAM_ADDR_U
Value
0
1
0000000 Reserved
Value Description
00h–
FFh
R/W
R/W
This byte defines the upper byte of the RAM address. On-chip
RAM is prioritized over all Memory Chip Selects. If the
enabled RAM and Chip Select addresses overlap, the
external Chip Select is not asserted.
P R E L I M I N A R Y
7
1
7
1
Description
On-chip general-purpose RAM is disabled.
On-chip general-purpose RAM is enabled.
R/W
R
6
0
6
1
R/W
R
5
0
5
1
R/W
R
4
0
4
1
R/W
R
3
0
3
1
Product Specification
Random Access Memory
R/W
R
2
0
2
1
eZ80F92/eZ80F93
R/W
R
1
0
1
1
R/W
R
0
0
0
1
195