EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 40

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

Table 3. Register Map (Continued)
PS015308-0404
Address
(hex)
Chip Select/Wait State Generator (continued)
00AE
00AF
00B0
00B1
00B2
00B3
On-Chip RAM Control
00B4
00B5
Serial Peripheral Interface (SPI) Block
00B8
00B9
00BA
00BB
00BC
Infrared Encoder/Decoder Block
00BF
Notes:
1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-
2. When the CPU reads this register, the current sampled value of the port is read.
3. Read Only if RTC registers are locked; Read/Write if RTC registers are unlocked.
4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After an
5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.
out reset, the Watch-Dog Timer Control register is reset to 20h.
RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b.
Mnemonic
CS2_LBR
CS2_UBR
CS2_CTL
CS3_LBR
CS3_UBR
CS3_CTL
RAM_CTL
RAM_ADDR_U
SPI_BRG_L
SPI_BRG_H
SPI_CTL
SPI_SR
SPI_TSR
SPI_RBR
IR_CTL
Name
Chip Select 2 Lower Bound Register
Chip Select 2 Upper Bound Register
Chip Select 2 Control Register
Chip Select 3 Lower Bound Register
Chip Select 3 Upper Bound Register
Chip Select 3 Control Register
RAM Control Register
RAM Address Upper Byte Register
SPI Baud Rate Generator Register—Low
Byte
SPI Baud Rate Generator Register—High
Byte
SPI Control Register
SPI Status Register
SPI Transmit Shift Register
SPI Receive Buffer Register
Infrared Encoder/Decoder Control
P R E L I M I N A R Y
Reset
(hex)
XX
XX
FF
00
00
00
00
00
00
80
02
00
04
00
00
Product Specification
eZ80F92/eZ80F93
Access
CPU
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R
Register Map
Page
195
195
137
139
139
140
141
141
131
69
70
71
69
70
71
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