R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 993

MCU 128KKB FLASH 48K 144-LQFP

R4F24568NVFQV

Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheets

Specifications of R4F24568NVFQV

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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H8S/2456, H8S/2456R, H8S/2454 Group
16.3.13 EP1 Data Register (EPDR1)
EPDR1 is a 128-byte receive FIFO buffer for endpoint 1. EPDR1 has a dual-buffer configuration,
and has a capacity of twice the maximum packet size. When one packet of data is received
successfully, EP1 FULL in interrupt flag register 2 is set, and the number of receive bytes is
indicated in the EP1 receive data size register. After the data has been read, the buffer that was
read is enabled to receive data again by writing 1 to the EP1 RDFN bit in trigger register 1. The
receive data in this FIFO buffer can be transferred by DMA. This FIFO buffer can be initialized
by means of EP1 CLR in FCLR register 1.
16.3.14 EP2 Data Register (EPDR2)
EPDR2 is a 128-byte transmit FIFO buffer for endpoint 2. EPDR2 has a dual-buffer configuration,
and has a capacity of twice the maximum packet size. When transmit data is written to this FIFO
buffer and EP2 PKTE in trigger register 1 is set, one packet of transmit data is fixed, and the dual-
FIFO buffer is switched over. The transmit data for this FIFO buffer can be transferred by DMA.
This FIFO buffer can be initialized by means of EP2 CLR in FCLR register 1.
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Bit
7 to 0
Bit
7 to 0
Bit Name
Bit Name
D7 to D0
D7 to D0
Initial
Value
Undefined W
Initial
Value
All 0
R/W
R
R/W
Description
Data register for endpoint 1 transfer
Description
Data register for endpoint 2 transfer
Section 16 USB Function Module (USB)
Page 963 of 1392

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