R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 689

MCU 128KKB FLASH 48K 144-LQFP

R4F24568NVFQV

Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheets

Specifications of R4F24568NVFQV

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
R4F24568NVFQV
Manufacturer:
REA
Quantity:
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Part Number:
R4F24568NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
H8S/2456, H8S/2456R, H8S/2454 Group
• PF2/LCAS/DQML*
• Modes 1, 2, 4, and 7 (EXPE = 1)
• Mode 7 (EXPE = 0)
Notes: 1. IRQ15 input when the ITS15 bit in ITSR is 0.
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Areas 2 to 5
SSU settings
PF2DDR
Pin function
Areas 2 to 5
SSU settings
PF2DDR
Pin function
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE
in SSER of SSU, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bits ABW5 to
ABW2 in ABWCR, bits SSI0S1 and SSI0S0 in PFCR5, and bit PF2DDR.
2. SSI0-C input when SSI0S1 and SSI0S0 = B'10 in PFCR5.
3. SSI0-C output when SSI0S1 and SSI0S0 = B'10 in PFCR5.
4. Not supported in the H8S/2456 Group.
synchronous DRAM
space area is 16-bit
DQML*
LCAS output
PF2 input
Any DRAM/
bus space
4
/IRQ15-A/SSI0-C (H8S/2456 Group and H8S/2456R Group)
0
4
(1) in table below
output
PF2 output
PF2 input
8-bit bus space, or areas 2 to 5 are all normal space
IRQ15-A interrupt input*
IRQ15-A interrupt input*
All DRAM/synchronous DRAM space areas are
(1) in table below
0
1
PF2 output
(2) in table below
SSI0-C input*
1
0
1
1
(2) in table
SSI0-C
input*
below
2
0
2
(3) in table below
SSI0-C output*
Section 10 I/O Ports
Page 659 of 1392
(3) in table
output*
SSI0-C
below
3
3

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