R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 683
![MCU 128KKB FLASH 48K 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Quantity
Price
Company:
Part Number:
R4F24568NVFQV
Manufacturer:
REA
Quantity:
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Part Number:
R4F24568NVFQV
Manufacturer:
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H8S/2456, H8S/2456R, H8S/2454 Group
10.14.1 Port F Data Direction Register (PFDDR)
The individual bits of PFDDR specify input or output for the pins of port F. PFDDR cannot be
read; if it is, an undefined value will be read.
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Bit
7
6
5
4
3
2
1
0
Bit Name
PF7DDR
PF6DDR
PF5DDR
PF4DDR
PF3DDR
PF2DDR
PF1DDR
PF0DDR
Initial
Value
1/0 *
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
Description
•
Modes 7 (when EXPE = 1), 1, 2, and 4
Pin PF7 functions as the φ output pin when the
corresponding PFDDR bit is set to 1, and as an input port
when the bit is cleared to 0.
Pin PF6 functions as the AS output pin when the ASOE
bit is set to 1. When the ASOE bit is cleared to 0, pin PF6
is an I/O port and its function can be switched with
PF6DDR.
Pins PF5 and PF4 are automatically designated as bus
control outputs (RD and HWR).
Pin PF3 functions as the LWR output pin when the
LWROE bit is set to 1. When the LWROE bit is cleared to
0, pin PF3 is an I/O port and its function can be switched
with PF3DDR.
Pins PF2 and PF1 function as bus control output pins
(LCAS and UCAS) when the appropriate bus controller
settings are made. Otherwise, operations differ between
the H8S/2456 and H8S/2456R Groups and H8S/2454
Group.
[H8S/2456 Group and H8S/2456R Group]
When pins PF2 and PF1 are general I/O ports, the
function can be switched with PFDDR.
Section 10 I/O Ports
Page 653 of 1392
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