R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 1116
![MCU 128KKB FLASH 48K 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 18 A/D Converter
18.7
18.7.1
Operation of the A/D converter can be disabled or enabled using the module stop control register.
The initial setting is for operation of the A/D converter to be halted. Register access is enabled by
clearing the module stop state. Set the CKS1 and CKS2 bits to 1 to set ADCLK to φ, and clear the
ADST, TRGS1, TRGS0, and EXTRGS bits all to 0 to disable A/D conversion when entering
module stop state after operation of the A/D converter. After that, set the module stop control
register after executing a dummy read by one word. For details, see section 24, Power-Down
Modes.
18.7.2
When this LSI enters software standby mode with A/D conversion enabled, the analog inputs are
retained, and the analog power supply current is equal to as during A/D conversion. If the analog
power supply current needs to be reduced in software standby mode, set the CKS1 and CKS2 bits
to 1 to set ADCLK to φ, and clear the ADST, TRGS1, TRGS0, and EXTRGS bits all to 0 to
disable A/D conversion. After that, enter software standby mode after executing a dummy read by
one word.
18.7.3
When the ADST bit has been cleared to 0, A/D converter stops in synchronization with the
ADCLK and then enters the standby sate. After the ADST bit has been cleared, the converter may
not actually make the transition to the standby state for up to 10 cycles (φ), so do not change the
channels of the ADCLK, motion mode, or analog input at this time.
When restarting the A/D converter right after the ADST bit has been cleared to 0, read the 16
bytes from ADDRA to ADDRH and then start the A/D converter by setting the ADST bit to 1. If
the converter is in single mode or one-cycle scan mode, however, the ADST bit can be set to 1 by
clearing the ADF bit to 0 after confirming that the ADF bit had been set to 1 on completion of the
previous round of conversion.
Page 1086 of 1392
Usage Notes
Module Stop Function Setting
A/D Input Hold Function in Software Standby Mode
Restarting the A/D Converter
H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
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