R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 1003

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2456, H8S/2456R, H8S/2454 Group
16.3.26 Stall Status Register 1 (STLSR1)
Bits 2 to 0 in STLSR1 are status bits that indicate the internal stall state of each endpoint (internal
status bits shown in figures 16.19 and 16.20). When a bit is 1, the corresponding endpoint is in
stall state. When a bit is 0, the corresponding endpoint is in normal operation state. Since these
bits are status bits, they cannot be cleared.
Bits 6 to 4 in STLSR1 are used to enable automatic stall clear for each endpoint.
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Bit
7
6
5
4
Bit Name
⎯
EP3 ASCE
EP2 ASCE
EP1 ASCE
Initial
Value
0
0
0
0
R/W
⎯
R/W
R/W
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
EP3 Automatic Stall Clear Enable
Setting the EP3 ASCE bit to 1 automatically clears the
EP3 stall setting bit (the EP3 STLS bit in EPSTL1)
after the stall handshake is returned to the host.
When the EP3 ASCE bit is set to 0, the stall setting bit
is not automatically cleared and must be cleared by
the users. To enable the automatic stall clear function,
make sure that the EP3 ASCE bit should be set to 1
before the EP3 STLS bit in EPSTL1 is set to 1.
EP2 Automatic Stall Clear Enable
Setting the EP2 ASCE bit to 1 automatically clears the
EP2 stall setting bit (the EP2 STLS bit in EPSTL1)
after the stall handshake is returned to the host.
When the EP2 ASCE bit is set to 0, the stall setting bit
is not automatically cleared and must be cleared by
the users. To enable the automatic stall clear function,
make sure that the EP2 ASCE bit should be set to 1
before the EP2 STLS bit in EPSTL1 is set to 1.
EP1 Automatic Stall Clear Enable
Setting the EP1 ASCE bit to 1 automatically clears the
EP1 stall setting bit (the EP1 STLS bit in EPSTL1)
after the stall handshake is returned to the host.
When the EP1 ASCE bit is set to 0, the stall setting bit
is not automatically cleared and must be cleared by
the users. To enable the automatic stall clear function,
make sure that the EP1 ASCE bit should be set to 1
before the EP1 STLS bit in EPSTL1 is set to 1.
Section 16 USB Function Module (USB)
Page 973 of 1392