R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 223
![MCU 128KKB FLASH 48K 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number:
R4F24568NVFQV
Manufacturer:
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Manufacturer:
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H8S/2456, H8S/2456R, H8S/2454 Group
6.4.4
This LSI can output chip select signals (CS0 to CS7) for areas 0 to 7. The signal outputs low when
the corresponding external space area is accessed. Figure 6.7 shows an example of CS0 to CS7
signals output timing.
Enabling or disabling of CS0 to CS7 signals output is set by the data direction register (DDR) bit
for the port corresponding to the CS0 to CS7 pins.
In expanded mode with on-chip ROM disabled, the CS0 pin is placed in the output state after a
reset. Pins CS1 to CS7 are placed in the input state after a reset and so the corresponding DDR bits
and PFCR0 bits should be set to 1 when outputting signals CS1 to CS7.
In expanded mode with on-chip ROM enabled, pins CS0 to CS7 are all placed in the input state
after a reset and so the corresponding DDR bits and PFCR0 bits should be set to 1 when
outputting signals CS0 to CS7.
When areas 2 to 5 are designated as DRAM space, outputs CS2 to CS5 are used as RAS signals.
When areas 2 to 5 are designated as continuous synchronous DRAM* space in the H8S/2456R
Group, outputs CS2, CS3, CS4, and CS5 are used as RAS, CAS, WE, and CLK signals.
Note: The A23E bit in PFCR1 should be cleared to 0 when CS7 signal is output in the H8S/2454
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
* The synchronous DRAM interface is not supported by the H8S/2456 Group and
Group.
Chip Select Signals
H8S/2454 Group.
φ
Address bus
CSn
Figure 6.7 CSn Signal Output Timing (n = 0 to 7)
T
1
Area n external address
Bus cycle
T
2
T
3
Section 6 Bus Controller (BSC)
Page 193 of 1392
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