R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 332

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
(b) Normal space access after DRAM space write access
(8)
Note: The synchronous DRAM interface is not supported by the H8S/2456 Group and H8S/2454
Page 302 of 1392
While the ICIS2 bit is set to 1 in BCR and a normal space read access occurs after DRAM
space write access, idle cycle is inserted in the first read cycle. The number of states of the idle
cycle to be inserted is in accordance with the setting of the IDLC bit. It does not depend on the
DRMI bit in DRACCR. Figure 6.90 shows an example of idle cycle operation when the ICIS2
bit is set to 1.
Idle Cycle in Case of Normal Space Access after Continuous Synchronous DRAM
Space Access:
Group.
UCAS, LCAS
Address bus
Figure 6.90 Example of Idle Cycle Operation after DRAM Write Access
HWR, LWR
Data bus
RAS
RD
φ
(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0)
T
p
DRAM space read
T
r
T
c1
T
c2
Idle cycle
T
i
External space read
T
1
T
2
H8S/2456, H8S/2456R, H8S/2454 Group
T
3
DRAM space read
T
REJ09B0467-0350 Rev. 3.50
c1
T
c2
Jul 07, 2010