R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 1154
![MCU 128KKB FLASH 48K 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R4F24568NVFQV
Manufacturer:
REA
Quantity:
15
Company:
Part Number:
R4F24568NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 20 Synchronous Serial Communication Unit (SSU)
(3)
Figure 20.7 shows an example of reception operation, and figure 20.8 shows a flowchart example
of data reception. When receiving data, the SSU operates as shown below.
After setting the RE bit to 1 and dummy-reading SSRDR, the SSU starts data reception.
In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a low
level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU receives
data in synchronization with the transfer clock.
When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is
stored in SSRDR. At this time, if the RIE bit in SSER is set to 1, an RXI interrupt is generated.
The RDRF bit is automatically cleared to 0 by reading SSRDR.
When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in
SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data
reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To
resume the reception, clear the ORER bit to 0.
Page 1124 of 1392
When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS = 0
Data Reception
User operation
LSI operation
SSCK
RDRF
Figure 20.7 (1) Example of Reception Operation (SSU Mode)
SCS
SSI
Dummy-read SSRDR0
Bit
0
Bit
(LSB first transmission)
1
Bit
2
1 frame
SSRDR0
Bit
3
Bit
4
Bit
5
Bit
6
REI interrupt
generated
Bit
7
Read SSRDR0
Bit
7
(MSB first transmission)
Bit
6
Bit
H8S/2456, H8S/2456R, H8S/2454 Group
5
SSRDR0
1 frame
Bit
4
Bit
3
Bit
2
REJ09B0467-0350 Rev. 3.50
REI interrupt
Bit
generated
1
Bit
0
Jul 07, 2010
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