R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 351
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Price
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Part Number:
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H8S/2456, H8S/2456R, H8S/2454 Group
This LSI has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4
channels.
7.1
•
•
•
• Activation sources: internal interrupt, external request, auto-request (depending on transfer
•
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Short address mode
⎯ Maximum of 4 channels can be used
⎯ Dual address mode or single address mode can be selected
⎯ In dual address mode, one of the two addresses, transfer source and transfer destination, is
⎯ In single address mode, transfer source or transfer destination address only is specified as
⎯ In single address mode, transfer can be performed in one bus cycle
⎯ Choice of sequential mode, idle mode, or repeat mode for dual address mode and single
Full address mode
⎯ Maximum of 2 channels can be used
⎯ Transfer source and transfer destination addresses as specified as 24 bits
⎯ Choice of normal mode or block transfer mode
mode)
⎯ Six compare match/input capture interrupts of 16-bit timer-pulse unit (TPU0 to TPU5)
⎯ Transmission complete interrupt and reception complete interrupt of serial communication
⎯ Conversion end interrupt of A/D converter (A/D_0)
⎯ EP1FIFO full interrupt and EP2FIFO empty interrupt of USB
⎯ External request
⎯ Auto-request
Selectable as short address mode or full address mode
16-Mbyte address space can be specified directly
Byte or word can be set as the transfer unit
Module stop state can be set.
specified as 24 bits and the other as 16 bits
24 bits
address mode
interface (SCI_0, SCI_1)
Features
Section 7 DMA Controller (DMAC)
Section 7 DMA Controller (DMAC)
Page 321 of 1392
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