R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 1000
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 16 USB Function Module (USB)
16.3.23 FIFO Clear Register 1 (FCLR1)
FCLR1 is a register to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all the
data in the corresponding FIFO buffer. Note that the corresponding interrupt flag is not cleared.
Do not clear a FIFO buffer during transfer.
Page 970 of 1392
Bit
7
6
5
4
3
2
1
0
Bit Name
⎯
⎯
⎯
⎯
⎯
EP3 CLR
EP2 CLR
EP1 CLR
Initial
Value
0
0
0
0
0
0
0
0
R/W
⎯
⎯
⎯
⎯
⎯
W
W
W
Description
Reserved
The write value should always be 0.
EP3 Clear
Writing 1 to this bit initializes the endpoint 3 transmit
FIFO buffer.
EP2 Clear
Writing 1 to this bit initializes both sides of the
endpoint 2 transmit FIFO buffer.
EP1 Clear
Writing 1 to this bit initializes both sides of the
endpoint 1 receive FIFO buffer.
H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
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