R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 320
![MCU 128KKB FLASH 48K 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 6 Bus Controller (BSC)
6.10
6.10.1
When this LSI accesses external address space, it can insert an idle cycle (T
in the following three cases: (1) when read accesses in different areas occur consecutively, (2)
when a write cycle occurs immediately after a read cycle, and (3) when a read cycle occurs
immediately after a write cycle. Insertion of a 1-state or 2-state idle cycle can be selected with the
IDLC bit in BCR. By inserting an idle cycle it is possible, for example, to avoid data collisions
between ROM, etc., with a long output floating time, and high-speed memory, I/O interfaces, and
so on.
(1)
If consecutive reads in different areas occur while the ICIS1 bit is set to 1 in BCR, an idle cycle is
inserted at the start of the second read cycle.
Figure 6.77 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each
being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in bus
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
Page 290 of 1392
Consecutive Reads in Different Areas
CS (area A)
CS (area B)
Address bus
Idle Cycle
Operation
Data bus
RD
φ
(a) No idle cycle insertion
(ICIS1 = 0)
T
1
Bus cycle A
Long output floating time
Figure 6.77 Example of Idle Cycle Operation
T
2
(Consecutive Reads in Different Areas)
T
3
Bus cycle B
T
1
T
2
Data collision
Address bus
CS (area A)
CS (area B)
Data bus
RD
φ
T
1
Bus cycle A
(b) Idle cycle insertion
H8S/2456, H8S/2456R, H8S/2454 Group
(ICIS1 = 1, initial value)
T
2
T
3
Idle cycle
i
REJ09B0467-0350 Rev. 3.50
) between bus cycles
T
Bus cycle B
i
T
1
T
2
Jul 07, 2010
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