R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 262
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
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Section 6 Bus Controller (BSC)
6.7.8
When DRAM is accessed, a RAS precharge time must be secured. With this LSI, one T
always inserted when DRAM space is accessed. From one to four T
setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of T
DRAM connected and the operating frequency of this LSI. Figure 6.37 shows the timing when
two T
cycles.
Page 232 of 1392
Read
Write
Note: n = 2 to 5
p
states are inserted. The setting of bits TPC1 and TPC0 is also valid for T
Precharge State Control
φ
Address bus
RASn (CSn)
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
Figure 6.37 Example of Timing with Two-State Precharge Cycle
T
p1
(RAST = 0, CAST = 0)
Row address
T
p2
High
High
T
r
H8S/2456, H8S/2456R, H8S/2454 Group
p
states can be selected by
T
c1
Column address
p
cycles according to the
REJ09B0467-0350 Rev. 3.50
p
states in refresh
T
c2
p
state is
Jul 07, 2010
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