R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 16

MCU 128KKB FLASH 48K 144-LQFP

R4F24568NVFQV

Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheets

Specifications of R4F24568NVFQV

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R4F24568NVFQV
Manufacturer:
REA
Quantity:
15
Part Number:
R4F24568NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
9.5
9.6
9.7
9.8
Section 10 I/O Ports........................................................................................... 509
10.1 Port 1.................................................................................................................................. 523
10.2 Port 2.................................................................................................................................. 549
10.3 Port 3.................................................................................................................................. 563
Page xvi of xxx
Operation ........................................................................................................................... 491
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
9.5.6
9.5.7
Procedures for Using DTC................................................................................................. 501
9.6.1
9.6.2
Examples of Use of the DTC ............................................................................................. 502
9.7.1
9.7.2
9.7.3
9.7.4
Usage Notes ....................................................................................................................... 507
9.8.1
9.8.2
9.8.3
9.8.4
9.8.5
10.1.1 Port 1 Data Direction Register (P1DDR).............................................................. 523
10.1.2 Port 1 Data Register (P1DR)................................................................................. 524
10.1.3 Port 1 Register (PORT1)....................................................................................... 524
10.1.4 Port 1 Open Drain Control Register (P1ODR) ..................................................... 525
10.1.5 Pin Functions ........................................................................................................ 526
10.2.1 Port 2 Data Direction Register (P2DDR).............................................................. 549
10.2.2 Port 2 Data Register (P2DR)................................................................................. 550
10.2.3 Port 2 Register (PORT2)....................................................................................... 550
10.2.4 Port 2 Open Drain Control Register (P2ODR) ..................................................... 551
10.2.5 Pin Functions ........................................................................................................ 552
10.3.1 Port 3 Data Direction Register (P3DDR).............................................................. 563
10.3.2 Port 3 Data Register (P3DR)................................................................................. 564
10.3.3 Port 3 Register (PORT3)....................................................................................... 564
Normal Mode........................................................................................................ 494
Repeat Mode......................................................................................................... 495
Block Transfer Mode ............................................................................................ 496
Chain Transfer ...................................................................................................... 497
Interrupt Sources................................................................................................... 498
Operation Timing.................................................................................................. 498
Number of DTC Execution States ........................................................................ 499
Activation by Interrupt.......................................................................................... 501
Activation by Software ......................................................................................... 501
Normal Mode........................................................................................................ 502
Chain Transfer ...................................................................................................... 503
Chain Transfer when Counter = 0......................................................................... 504
Software Activation .............................................................................................. 506
Module Stop Function Setting .............................................................................. 507
On-Chip RAM ...................................................................................................... 507
DTCE Bit Setting.................................................................................................. 507
DMAC Transfer End Interrupt.............................................................................. 507
Chain Transfer ...................................................................................................... 507

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