R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 14

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 DMA Controller (DMAC)................................................................. 321
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Page xiv of xxx
6.15.3 External Bus Release Function and CBR Refreshing/Auto Refreshing................ 318
6.15.4 BREQO Output Timing ........................................................................................ 319
6.15.5 Notes on Usage of the Synchronous DRAM ........................................................ 319
Features.............................................................................................................................. 321
Input/Output Pins............................................................................................................... 323
Register Descriptions ......................................................................................................... 324
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
Activation Sources............................................................................................................. 351
7.4.1
7.4.2
7.4.3
Operation ........................................................................................................................... 353
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10 DMA Transfer (Single Address Mode) Bus Cycles ............................................. 387
7.5.11 Write Data Buffer Function .................................................................................. 394
7.5.12 Multi-Channel Operation...................................................................................... 395
7.5.13 Relation between DMAC and External Bus Requests,
7.5.14 DMAC and NMI Interrupts .................................................................................. 398
7.5.15 Forced Termination of DMAC Operation ............................................................ 399
7.5.16 Clearing Full Address Mode................................................................................. 400
Interrupt Sources................................................................................................................ 401
Usage Notes ....................................................................................................................... 402
Memory Address Registers (MARA and MARB)................................................ 326
I/O Address Registers (IOARA and IOARB)....................................................... 327
Execute Transfer Count Registers (ETCRA and ETCRB) ................................... 328
DMA Control Registers (DMACRA and DMACRB) .......................................... 329
DMA Band Control Registers H and L (DMABCRH and DMABCRL).............. 337
DMA Write Enable Register (DMAWER)........................................................... 348
DMA Terminal Control Register (DMATCR) ..................................................... 350
Activation by Internal Interrupt Request .............................................................. 352
Activation by External Request ............................................................................ 353
Activation by Auto-Request ................................................................................. 353
Transfer Modes..................................................................................................... 353
Sequential Mode ................................................................................................... 356
Idle Mode.............................................................................................................. 358
Repeat Mode......................................................................................................... 361
Single Address Mode............................................................................................ 365
Normal Mode........................................................................................................ 368
Block Transfer Mode ............................................................................................ 371
Basic Bus Cycles .................................................................................................. 377
DMA Transfer (Dual Address Mode) Bus Cycles................................................ 378
Refresh Cycles, and EXDMAC ............................................................................ 397