R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 509

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2456, H8S/2456R, H8S/2454 Group
9.2
DTC has the following registers.
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These six registers cannot be directly accessed from the CPU. When activated, the DTC reads a
set of register information that is stored in an on-chip RAM to the corresponding DTC registers
and transfers data. After the data transfer, it writes a set of updated register information back to the
RAM.
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9.2.1
MRA selects the DTC operating mode.
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Bit
7
6
DTC mode register A (MRA)
DTC mode register B (MRB)
DTC source address register (SAR)
DTC destination address register (DAR)
DTC transfer count register A (CRA)
DTC transfer count register B (CRB)
DTC enable registers A to I (DTCERA to DTCERI)
DTC vector register (DTVECR)
DTC control register (DTCCR)
Bit Name
SM1
SM0
Register Descriptions
DTC Mode Register A (MRA)
Initial Value
Undefined
Undefined
R/W
⎯
⎯
Description
Source Address Mode 1 and 0
These bits specify an SAR operation after a data
transfer.
0x: SAR is fixed
10: SAR is incremented after a transfer
11: SAR is decremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
(by –1 when Sz = 0; by –2 when Sz = 1)
Section 9 Data Transfer Controller (DTC)
Page 479 of 1392