R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 635

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Bit
Bit Name Initial
Value
R/W Description
•
•
Modes 7 (when EXPE = 1) and 4
For pins PA6 to PA0, when the corresponding bit of A22E to
A16E is set to 1, setting a PADDR bit to 1 makes the
corresponding pin an address output, while clearing the bit to
0 makes the corresponding pin an input port. Clearing one of
bits A22E to A16E to 0 makes the corresponding pin an I/O
port, and its function can be switched with PADDR.
When A23E is 1, the PA7 pin functions as an address output
pin when the PA7DDR bit is set to 1, and as an input port
when the bit is cleared to 0.
When A23E is 0, operations differ between the H8S/2456
and H8S/2456R Groups and H8S/2454 Group.
[H8S/2456 Group and H8S/2456R Group]
When the PA7 pin is a general I/O port, the function can be
switched with PA7DDR.
[H8S/2454 Group]
When the CS output enable bit (CS7E) is 1, the PA7 pin
functions as a CS output pin when the PA7DDR bit is set to
1, and as an input port when the bit is cleared to 0. When the
CS output enable bit (CS7E) is 0 and the PA7 pin is a
general I/O port, the function can be switched with PA7DDR.
Mode 7 (when EXPE = 0)
Port A is an I/O port, and its pin functions can be switched
with PADDR.
Section 10 I/O Ports
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