R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 416
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 7 DMA Controller (DMAC)
Figure 7.25 shows an example of block transfer mode transfer activated by DREQ pin low level.
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the dead cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
Page 386 of 1392
[1]
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the dead cycle is completed.
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
φ
DREQ
Address
bus
DMA
control
Channel
Figure 7.25 Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
Idle
Bus release
[1]
Request
of 2 cycles
Minimum
[2]
Read
[3]
Transfer source
Request clear period
DMA
read
Write
1 block transfer
Transfer destination
DMA
write
Acceptance resumes
Dead
[4]
Request
DMA
dead
of 2 cycles
Minimum
Idle
[5]
release
Bus
Read
[6]
Transfer source
Request clear period
DMA
read
H8S/2456, H8S/2456R, H8S/2454 Group
Write
1 block transfer
Transfer destination
REJ09B0467-0350 Rev. 3.50
DMA
write
Dead
Acceptance resumes
DMA
dead
[7]
Jul 07, 2010
Idle
release
Bus
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