R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 1058
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 17 I2C Bus Interface 2 (IIC2)
17.3.2
ICCRB is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA
pin, monitors the SCL pin, and controls reset in I
Page 1028 of 1392
Bit
7
6
5
4
3
2
Bit Name
BBSY
SCP
SDAO
⎯
SCLO
⎯
I
2
C Bus Control Register B (ICCRB)
0
1
1
1
1
1
Initial Value
R/W
R/W
R/W
R
R/W
R
⎯
Description
Bus Busy
This bit enables to confirm whether the I
occupied or released and to issue start and stop
conditions in master mode. This bit is set to 1
when the SDA level changes from high to low
under the condition of SCL = high, assuming that
the start condition has been issued. This bit is
cleared to 0 when the SDA level changes from low
to high under the condition of SCL = high,
assuming that the stop condition has been issued.
Write 1 to BBSY and 0 to SCP to issue a start
condition. Follow this procedure when also re-
transmitting a start condition. Write 0 to BBSY and
0 to SCP to issue a stop condition. To issue a
start/stop condition, use the MOV instruction.
Start Condition/Stop Condition Prohibit
The SCP bit controls the issue of start/stop
conditions in master mode.
To issue a start condition, write 1 in BBSY and 0
in SCP. A retransmit start condition is issued in
the same way. To issue a stop condition, write 0 in
BBSY and 0 in SCP. This bit is always read as 1.
If 1 is written, the data is not stored.
This bit monitors SDA output level. When reading
and SDA0 is 1, the SDA pin outputs high. When
reading and SDA0 is 0, the SDA pin outputs low.
The write value should always be 1.
Reserved
The write value should always be 1.
This bit monitors SCL output level. When reading
and SCLO is 1, the SCL pin outputs high. When
reading and SCLO is 0, the SCL pin outputs low.
Reserved
This bit is always read as 1.
2
C control.
H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
2
C bus is
Jul 07, 2010
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