R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 178

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 5 Interrupt Controller
5.7.2
Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions is executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.
5.7.3
There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt
controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask
level with an LDC, ANDC, ORC, or XORC instruction.
5.7.4
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the transfer is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction. Therefore, if an interrupt is generated during execution
of an EEPMOV.W instruction, the following coding should be used.
5.7.5
When the ITSR setting is changed, an edge occurs internally and the IRQnF bit (n = 0 to 15 for
H8S/2456 Group, n = 0 to 7 for H8S/2454 Group) of ISR may be set to 1 at the unintended timing
if the selected pin level before the change is different from the selected pin level after the change.
If the IRQn interrupt request (n = 0 to 15 for H8S/2456 Group, n = 0 to 7 for H8S/2454 Group) is
enabled, the interrupt exception handling is executed. To prevent the unintended interrupt, ITSR
setting should be changed while the IRQn interrupt request is disabled, then the IRQnF bit should
be cleared to 0.
Page 148 of 1392
L1:
Instructions that Disable Interrupts
Times when Interrupts are Disabled
Interrupts during Execution of EEPMOV Instruction
Change of IRQ Pin Select Register (ITSR) Setting
EEPMOV.W
MOV.W
BNEL1
R4,R4
H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010