R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 701

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2456, H8S/2456R, H8S/2454 Group
10.15.4 Port G Open Drain Control Register (PGODR)
PGODR specifies the output type of each port G pin.
Notes: 1. Not supported in the H8S/2456 and 2454 Groups.
10.15.5 Pin Functions
Port G pins also function as the pins for bus control signal I/Os. The correspondence between the
register specification and the pin functions is shown below.
• PG6/BREQ-A
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Bit
7
6
5
4
3
2
1
0
Operating mode
EXPE
BRLE
BREQS
PG6DDR
Pin function
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit BRLE in BCR of the bus controller, bit BREQS in PFCR4, and bit
PG6DDR.
Bit Name
⎯
PG6ODR
PG5ODR
PG4ODR
PG3ODR
PG2ODR
PG1ODR
PG0ODR
2. Not supported in the H8S/2456 and 2456R Groups.
BRLE = 1 and
input
PG6
BRLE = 0 or
BREQS = 1
0
Initial Value
0
0
0
0
0
0
0
0
output
PG6
1
1, 2, 4
⎯
BREQS = 0
BRLE = 1
BREQ-A
R/W
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
input
and
⎯
Description
Reserved
This bit is always read as 0. Only the initial value
should be written to this bit.
When not specified for BACK-A, BREQO-A, CS0,
CS1, CS2, CS3, CS4*
CAS*
corresponding pin an NMOS open-drain output pin,
while clearing a PGODR bit to 0 makes the
corresponding pin a CMOS output pin.
input
PG6
0
1
output, setting a PGODR bit to 1 makes the
⎯
0
output
PG6
1
BRLE = 1 and
input
PG6
BRLE = 0 or
BREQS = 1
2
0
, RAS2, RAS3, RAS*
7
output
PG6
1
1
Section 10 I/O Ports
BREQ-A input
Page 671 of 1392
BREQS = 0
BRLE = 1
and
⎯
1
, or