R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 984

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 USB Function Module (USB)
16.3.2
IFR1, together with interrupt flag registers 0 and 2 (IFR0 and IFR2), indicates interrupt status
information required by the application. When an interrupt source is generated, the corresponding
bit is set to 1. And then this bit, in combination with interrupt enable register 1 (IER1), generates
an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits.
Page 954 of 1392
Bit
7
6
5
4
3
2
1
0
Interrupt Flag Register 1 (IFR1)
Bit Name
⎯
⎯
⎯
SOF
SETUP TS
EP0o TS
EP0i TR
EP0i TS
Initial
Value
0
0
0
0
0
0
0
0
R/W
⎯
⎯
⎯
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
SOF Packet Detection
This bit is set to 1 when the Start Of Frame (SOF)
packet is detected.
Setup Command Receive Complete
This bit is set to 1 when endpoint 0 receives
successfully a setup command requiring decoding on
the application side, and returns an ACK handshake to
the host.
EP0o Receive Complete
This bit is set to 1 when endpoint 0 receives data from
the host successfully, stores the data in the FIFO
buffer, and returns an ACK handshake to the host.
EP0i Transfer Request
This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 0 is
received from the host. A NAK handshake is returned
to the host until data is written to the FIFO buffer and
packet transmission is enabled.
EP0i Transmit Complete
This bit is set when data is transmitted to the host from
endpoint 0 and an ACK handshake is returned.
H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010