R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 421
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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H8S/2456, H8S/2456R, H8S/2454 Group
(3)
Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected.
Figure 7.30 shows an example of single address mode transfer activated by the DREQ pin falling
edge.
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Figure 7.30 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer
Address bus
[1]
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the single
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
DMA control
DREQ Pin Falling Edge Activation Timing
Channel
DREQ
DACK
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and
the request is held.)
φ
Idle
[1]
Request
Bus release
Minimum of
2 cycles
[2]
[3]
Single
Request clear
Transfer source/
DMA single
period
destination
Acceptance resumes
Idle
[4]
Request
Bus release
Minimum of
2 cycles
[5]
[6]
Single
DMA single
Request clear
Transfer source/
Section 7 DMA Controller (DMAC)
destination
period
Acceptance resumes
Idle
[7]
Bus release
Page 391 of 1392
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