R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 395
![MCU 128KKB FLASH 48K 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Price
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R4F24568NVFQV
Manufacturer:
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Quantity:
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Manufacturer:
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H8S/2456, H8S/2456R, H8S/2454 Group
7.5.5
Single address mode can only be specified for channel B. This mode can be specified by setting
the SAE bit in DMABCRH to 1 in short address mode.
One address is specified by MAR, and the other is set automatically to the data transfer
acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACR.
Table 7.8 summarizes register functions in single address mode.
Table 7.8
MAR specifies the start address of the transfer source or transfer destination as 24 bits. IOAR is
invalid; in its place the strobe for external devices (DACK) is output.
Figure 7.9 illustrates operation in single address mode (when sequential mode is specified).
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Register
23
15
Single Address Mode
DACK pin
Register Functions in Single Address Mode
ETCR
MAR
0
0
Source
address
register
Write
strobe
Transfer counter
DTDIR = 0 DTDIR = 1 Initial Setting
Function
Destination
address
register
Read
strobe
Start address of
transfer destination
or transfer source
(Set automatically
by SAE bit in
DMABCRH; IOAR
is invalid)
Number of transfers See sections 7.5.2,
Section 7 DMA Controller (DMAC)
Operation
See sections 7.5.2,
Sequential Mode,
7.5.3, Idle Mode,
and 7.5.4, Repeat
Mode.
Strobe for external
device
Sequential Mode,
7.5.3, Idle Mode,
and 7.5.4, Repeat
Mode.
Page 365 of 1392
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