R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 1163
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
[1]
[2]
[3]
[4]
Note: Hatching boxes represent SSU internal operations.
Data transferred from SSTDR to SSTRSR
Set TDRE to 1 to start transmission
Confirm that TEND is cleared to 0
Write transmit data to SSTDR
TDRE automatically cleared
Consecutive data transmission?
Clear TE in SSER to 0
Read TDRE in SSSR
Read TEND in SSSR
Clear TEND to 0
quantum elapsed?
End transmission
Initial setting
One bit time
TDRE = 1?
TEND = 1?
Yes
Yes
Yes
Figure 20.14 Flowchart Example of Transmission Operation
No
Start
(Clock Synchronous Communication Mode)
Yes
No
No
No
[4][1] Initial setting:
[2] Check that the SSU state and write transmit data:
[3] Procedure for consecutive data transmission:
[4] Procedure for data transmission end:
Specify the transmit data format.
Write transmit data to SSTDR after reading and confirming
that the TDRE bit is 1. The TDRE bit is automatically cleared
to 0 and transmission is started by writing data to SSTDR.
meaning that SSTDR is ready to be written to. After that, data
can be written to SSTDR. The TDRE bit is automatically
cleared to 0 by writing data to SSTDR.
To end data transmission, confirm that the TEND bit is cleared
to 0. After completion of transmitting the last bit, clear the TE
bit to 0.
To continue data transmission, confirm that the TDRE bit is 1
Section 20 Synchronous Serial Communication Unit (SSU)
Page 1133 of 1392
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