R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 1183

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2456, H8S/2456R, H8S/2454 Group
22.4
The following describes the software commands. A command or data should be read or written in
16-bit units at an even address in the user ROM or data flash area. When a command code is
written, the lower eight bits (D7 to D0) are ignored.
Table 22.5 List of Software Commands
[Legend]
SRD:
WA0:
WA1:
WD0:
WD1:
BA:
x:
xx:
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Software
Command
Read array
Read status
register
Clear status
register
Program
Block erase
Block blank
check
Status register data (D7 to D0)
Address to write the lower word (the address for the first bus cycle must be the same even
Address to write the upper word
Lower word of write data (16 bits)
Upper word of write data (16 bits)
Lowest address of the block (note that this should be an even address).
(i.e. H'0000 0000 for block 0, H'0001 0000 for block 1)
A desired even address in user ROM, data flash, or user boot ROM.
Lower eight bits of command code (ignored)
address as that for the second bus cycle).
Software Commands
Mode Address
Write
Write
Write
Write
Write
Write
First Bus Cycle
x
x
x
WA0
x
x
Data
(D15 to
D0)
H'FFxx
H'70xx
H'50xx
H'41xx
H'20xx
H'25xx
Mode Address
Read
Write
Write
Write
Second Bus Cycle
x
WA0
BA
BA
Data
(D15 to
D0)
SRD
WD0
H'D0xx
H'D0xx
Mode Address
Write
Third Bus Cycle
Section 22 Flash Memory
WA1
Page 1153 of 1392
Data
(D15 to
D0)
WD1