R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 371

MCU 128KKB FLASH 48K 144-LQFP

R4F24568NVFQV

Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheets

Specifications of R4F24568NVFQV

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R4F24568NVFQV
Manufacturer:
REA
Quantity:
15
Part Number:
R4F24568NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Bit
13, 12
11
10
Bit Name
DTA1
Initial Value
All 0
0
0
R/W
R/W
R/W
R/W
Description
Reserved
These bits can be read from or written to.
However, the write value should always be 0.
Data Transfer Acknowledge 1
These bits enable or disable clearing when DMA
transfer is performed for the internal interrupt
source selected by the DTF3 to DTF0 bits in
DMACR of channel 1.
It the DTA1 bit is set to 1 when DTE1 = 1, the
internal interrupt source is cleared automatically
by DMA transfer. When DTE1 = 1 and DTA1 = 1,
the internal interrupt source does not issue an
interrupt request to the CPU or DTC.
It the DTA1 bit is cleared to 0 when DTE1 = 1, the
internal interrupt source is not cleared when a
transfer is performed, and can issue an interrupt
request to the CPU or DTC in parallel. In this
case, the interrupt source should be cleared by
the CPU or DTC transfer.
When DTE1 = 0, the internal interrupt source
issues an interrupt request to the CPU or DTC
regardless of the DTA1 bit setting.
The state of the DTME1 bit does not affect the
above operations.
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
Section 7 DMA Controller (DMAC)
Page 341 of 1392

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