R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 634
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 10 I/O Ports
10.9.1
The individual bits of PADDR specify input or output for the pins of port A. PADDR cannot be
read; if it is, an undefined value will be read.
Page 604 of 1392
Bit
7
6
5
4
3
2
1
0
Bit Name Initial
PA7DDR
PA6DDR
PA5DDR
PA4DDR
PA3DDR
PA2DDR
PA1DDR
PA0DDR
Port A Data Direction Register (PADDR)
Value
0
0
0
0
0
0
0
0
R/W Description
W
W
W
W
W
W
W
W
•
Modes 1 and 2
Pins PA4 to PA0 are address outputs.
For pins PA6 and PA5, when the corresponding bit of A22E
and A21E is set to 1, setting a PADDR bit to 1 makes the
corresponding pin an address output, while clearing the bit to
0 makes the corresponding pin an input port. Clearing one of
bits A22E and A21E to 0 makes the corresponding pin an I/O
port, and its function can be switched with PADDR.
When A23E is 1, the PA7 pin functions as an address output
pin when the PA7DDR bit is set to 1, and as an input port
when the bit is cleared to 0.
When A23E is 0, operations differ between the H8S/2456
and H8S/2456R Groups and H8S/2454 Group.
[H8S/2456 Group and H8S/2456R Group]
When the PA7 pin is a general I/O port, the function can be
switched with PA7DDR.
[H8S/2454 Group]
When the CS output enable bit (CS7E) is 1, the PA7 pin
functions as a CS output pin when the PA7DDR bit is set to
1, and as an input port when the bit is cleared to 0. When the
CS output enable bit (CS7E) is 0 and the PA7 pin is a
general I/O port, the function can be switched with PA7DDR.
H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
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