R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 782
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.4.3
Buffer operation, provided for channels 0, 3, 6, and 9, enables TGRC and TGRD to be used as
buffer registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or a compare match register.
Table 11.29 shows the register combinations used in buffer operation.
Table 11.29 Register Combinations in Buffer Operation
•
Page 752 of 1392
Unit
0
1
Buffer register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 11.13.
When TGR is an output compare register
Buffer Operation
Channel
0
3
6
9
Figure 11.13 Compare Match Buffer Operation
Compare match signal
Timer General Register
TGRA_0
TGRB_0
TGRA_3
TGRB_3
TGRA_6
TGRB_6
TGRA_9
TGRB_9
Timer general
register
Comparator
H8S/2456, H8S/2456R, H8S/2454 Group
Buffer Register
TGRC_0
TGRD_0
TGRC_3
TGRD_3
TGRC_6
TGRD_6
TGRC_9
TGRD_9
REJ09B0467-0350 Rev. 3.50
TCNT
Jul 07, 2010
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