R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 1110
![MCU 128KKB FLASH 48K 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Quantity
Price
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Part Number:
R4F24568NVFQV
Manufacturer:
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Quantity:
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R4F24568NVFQV
Manufacturer:
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Quantity:
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Section 18 A/D Converter
18.4.3
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
1, then starts A/D conversion. Figure 18.6 shows the A/D conversion timing. Tables 18.5 and 18.6
show the A/D conversion time.
As shown in figure 18.6, the A/D conversion time (t
time (t
write access to ADCSR. The total conversion time therefore varies within the ranges indicated in
tables 18.5 and 18.6.
In scan mode, the values given in tables 18.5 and 18.6 apply to the first conversion time. The
values given in table 18.7 apply to the second and subsequent conversions. In either case, bit
EXCKS in ADCSR, and bits CKS1 and CKS0 in ADCR should be set so that the conversion time
is within the ranges indicated by the A/D conversion characteristics.
Page 1080 of 1392
D
) and the input sampling time (t
Input Sampling and A/D Conversion Time
Address
Write signal
Input sampling
timing
ADF
φ
[Legend]
(1):
(2):
t
t
t
D:
SPL
CONV
:
: A/D conversion time
ADCSR write cycle
ADCSR address
A/D conversion start delay time
Input sampling time
Figure 18.6 A/D Conversion Timing
(1)
(2)
t
D
SPL
). The length of t
t
SPL
D
) passes after the ADST bit in ADCSR is set to
CONV
t
CONV
) includes the A/D conversion start delay
D
varies depending on the timing of the
H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
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