R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 900
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 15 Serial Communication Interface (SCI, IrDA)
Page 870 of 1392
Bit
4
3
2
Bit Name
RE
MPIE
TEIE
0
0
0
Initial Value
R/W
R/W
R/W
R/W
Description
Receive Enable
When this bit is set to 1, reception is enabled.
Serial reception is started in this state when a start
bit is detected in asynchronous mode or serial
clock input is detected in clocked synchronous
mode. SMR setting must be performed to decide
the transfer format before setting the RE bit to 1.
Clearing the RE bit to 0 does not affect the RDRF,
FER, PER, and ORER flags, which retain their
states.
Multiprocessor Interrupt Enable (enabled only
when the MP bit in SMR is 1 in asynchronous
mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of
the RDRF, FER, and ORER status flags in SSR is
prohibited. On receiving data in which the
multiprocessor bit is 1, this bit is automatically
cleared and normal reception is resumed. For
details, refer to section 15.5, Multiprocessor
Communication Function.
When receive data including MPB = 0 in SSR is
received, receive data transfer from RSR to RDR,
receive error detection, and setting of the RDRF,
FER, and ORER flags in SSR , is not performed.
When receive data including MPB = 1 is received,
the MPB bit in SSR is set to 1, the MPIE bit is
cleared to 0 automatically, and generation of RXI
and ERI interrupts (when the TIE and RIE bits in
SCR are set to 1) and FER and ORER flag setting
is enabled.
Transmit End Interrupt Enable
When this bit is set to 1, TEI interrupt request is
enabled. TEI cancellation can be performed by
reading 1 from the TDRE flag in SSR, then
clearing it to 0 and clearing the TEND flag to 0, or
by clearing the TEIE bit to 0.
H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
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