R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 1042

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 USB Function Module (USB)
16.8
16.8.1
DMA transfer can be performed for endpoints 1 and 2 in this module. Note that word or longword
data cannot be transferred.
When endpoint 1 holds at least one byte of valid receive data, a DMA request for endpoint 1 is
generated. When endpoint 2 holds no valid data, a DMA request for endpoint 2 is generated.
If the DMA transfer is enabled by setting the EP1 DMAE bit in the DMA transfer setting register
to 1, zero-length data reception at endpoint 1 is ignored. When the DMA transfer is enabled, the
EP1 RDFN bit and EP2 PKTE bit do not need to be set to 1 in TRG1. (Note that the PKTE bit in
TRG1 must be set to 1 when the transfer data is less than the maximum number of bytes). When
all the data received at EP1 is read, the FIFO automatically enters the EMPTY state. When the
maximum number of bytes (64 bytes) are written to the EP2 FIFO, the FIFO automatically enters
the FULL state, and the data in the FIFO can be transmitted (see figures 16.21 and 16.22).
16.8.2
The on-chip DMAC should be set for USB requests (using the DREQ signal), low-level input
activation, byte size, full-address mode transfer, and the DTA bit = 1 in the DMABCR register.
The on-chip DMAC will then be stopped after transfer has been completed the specified number
of times. However, note that the DREQ signal continues to be asserted (held at the low level)
regardless of the state of the DMAC when the DMA transfer requests still remains in this module.
Page 1012 of 1392
DMA Transfer
Overview
Setting for the On-chip DMAC
H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010