R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 985

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2456, H8S/2456R, H8S/2454 Group
16.3.3
IFR2, together with interrupt flag registers 0 and 1, (IFR0 and IFR1), indicates interrupt status
information required by the application. When an interrupt source is generated, the corresponding
bit is set to 1. And then this bit, in combination with interrupt enable register 2 (IER2), generates
an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits.
However, since EP2 EMPTY, EP2 ALLEMP, and EP1 FULL are status bits, these bits cannot be
cleared.
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Bit
7
6
5
4
3
2
1
Interrupt Flag Register 2 (IFR2)
Bit Name
⎯
⎯
EP3 TR
EP3 TS
EP2 TR
EP2 EMPTY 1
EP2
ALLEMP
Initial
Value
0
0
0
0
0
1
R/W
⎯
⎯
R/W
R/W
R/W
R
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
EP3 Transfer Request
This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 3 is
received from the host. A NAK handshake is returned
to the host until data is written to the FIFO buffer and
packet transmission is enabled.
EP3 Transmit Complete
This bit is set when data is transmitted to the host from
endpoint 3 and an ACK handshake is returned.
EP2 Transfer Request
This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 2 is
received from the host. A NAK handshake is returned
to the host until data is written to the FIFO buffer and
packet transmission is enabled.
EP2 FIFO Empty
This bit is set when at least one of the dual endpoint 2
transmit FIFO buffers is ready for transmit data to be
written.
This is a status bit and cannot be cleared.
EP2 FIFO All Empty
This bit is set when both of the dual endpoint 2 transmit
FIFO buffers are empty.
This is a status bit and cannot be cleared.
Section 16 USB Function Module (USB)
Page 955 of 1392