R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 1051

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2456, H8S/2456R, H8S/2454 Group
This LSI has a four-channel I
The I
interface functions (Rev. 0.3) for standard-mode and fast-mode. The register configuration that
controls the I
Figure 17.1 shows a block diagram of the I
I/O pin connections to external circuits.
17.1
•
•
•
•
•
•
•
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically. If transmission/reception is not yet possible, set the SCL to low until
preparations are completed.
Transmit-data-empty (including slave-address match), transmit-end, receive-data-full
(including slave-address match), arbitration lost, NACK detection, and stop condition
detection
Two pins, SCL and SDA pins function as NMOS open-drain outputs.
Continuous transmission/reception
Start and stop conditions generated automatically in master mode
Selection of acknowledge output levels when receiving
Automatic loading of acknowledge bit when transmitting
Bit synchronization/wait function
Six interrupt sources
Direct bus drive
2
C bus interface conforms to and provides a subset of the NXP I
Features
2
C bus differs partly from the NXP configuration, however.
Section 17 I
2
C bus interface.
2
C Bus Interface 2 (IIC2)
2
C bus interface 2. Figure 17.2 shows an example of
2
Section 17 I2C Bus Interface 2 (IIC2)
C bus (inter-IC bus)
Page 1021 of 1392