R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 271

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2456, H8S/2456R, H8S/2454 Group
(2)
Even when burst operation is selected, it may happen that access to DRAM space is not
continuous, but is interrupted by access to another space. In this case, if the RAS signal is held low
during the access to the other space, burst operation can be resumed when the same row address in
DRAM space is accessed again.
• RAS Down Mode
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
To select RAS down mode, set both the RCDM bit and the BE bit to 1 in DRAMCR. If access
to DRAM space is interrupted and another space is accessed, the RAS signal is held low
during the access to the other space, and burst access is performed when the row address of the
next DRAM space access is the same as the row address of the previous DRAM space access.
Figure 6.44 shows an example of the timing in RAS down mode.
Note, however, that the RAS signal will go high if:
⎯ a refresh operation is initiated in the RAS down state
⎯ self-refreshing is performed
⎯ the chip enters software standby mode
⎯ the external bus is released
⎯ the RCDM bit or BE bit is cleared to 0
If a transition is made to the all-module-clocks-stopped mode in the RAS down state, the clock
will stop with RAS low. To enter the all-module-clocks-stopped mode with RAS high, the
RCDM bit must be cleared to 0 before executing the SLEEP instruction.
RAS Down Mode and RAS Up Mode
Section 6 Bus Controller (BSC)
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