R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 261

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2456, H8S/2456R, H8S/2454 Group
If a row address hold time or read access time is necessary, making a setting in bits RCD1 and
RCD0 in DRACCR allows from one to three T
to be inserted between the T
the column address is output. Use the setting that gives the optimum row address signal hold time
relative to the falling edge of the RAS signal according to the DRAM connected and the operating
frequency of this LSI. Figure 6.36 shows an example of the timing when one T
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Read
Write
Note: n = 2 to 5
Figure 6.36 Example of Timing with One Row Address Output Maintenance State
φ
Address bus
RASn (CSn)
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
r
cycle, in which the RAS signal goes low, and the T
T
p
(RAST = 0, CAST = 0)
Row address
T
r
rw
states, in which row address output is maintained,
T
rw
High
High
T
Column address
c1
Section 6 Bus Controller (BSC)
rw
c1
state is set.
cycle, in which
T
c2
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