R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 841
![MCU 128KKB FLASH 48K 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R4F24568NVFQV
Manufacturer:
REA
Quantity:
15
Company:
Part Number:
R4F24568NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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H8S/2456, H8S/2456R, H8S/2454 Group
12.4.2
Figure 12.4 shows a sample procedure for setting up normal pulse output.
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
TPU setup
Port and
PPG setup
TPU setup
Sample Setup Procedure for Normal Pulse Output
Figure 12.4 Setup Procedure for Normal Pulse Output (Example)
Set counting operation
Select interrupt request
Select TGR functions
Set initial output data
Select output trigger
Enable pulse output
Normal PPG output
Compare match?
Set TGRA value
Set next pulse
Set next pulse
Start counter
output data
output data
Yes
No
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[1] Set TIOR to make TGRA an output
[2] Set the PPG output trigger period.
[3] Select the counter clock source with
[4] Enable the TGIA interrupt in TIER.
[5] Set the initial output values in
[6] Set the DDR and NDER bits for the
[7] Select the TPU compare match
[8] Set the next pulse output values in
[9] Set the CST bit in TSTR to 1 to start
[10] At each TGIA interrupt, set the next
compare register (with output
disabled).
bits TPSC2 to TPSC0 in TCR.
Select the counter clear source with
bits CCLR2 to CCLR0.
The DTC or DMAC can also be set
up to transfer data to NDR.
PODR.
pins to be used for pulse output to 1.
event to be used as the output
trigger in PCR.
NDR.
the TCNT counter.
output values in NDR.
Section 12 Programmable Pulse Generator (PPG)
Page 811 of 1392
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