R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 1129

MCU 128KKB FLASH 48K 144-LQFP

R4F24568NVFQV

Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheets

Specifications of R4F24568NVFQV

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Manufacturer
Quantity
Price
Part Number:
R4F24568NVFQV
Manufacturer:
REA
Quantity:
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Part Number:
R4F24568NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
H8S/2456, H8S/2456R, H8S/2454 Group
This LSI has one channel of synchronous serial communication unit (SSU). The SSU has master
mode in which this LSI outputs clocks as a master device for synchronous serial communication
and slave mode in which clocks are input from an external device for synchronous serial
communication. Synchronous serial communication can be performed with devices having
different clock polarity and clock phase. Figure 20.1 is a block diagram of the SSU.
20.1
• Choice of SSU mode and clock synchronous mode
• Choice of master mode and slave mode
• Choice of standard mode and bidirectional mode
• Synchronous serial communication with devices with different clock polarity and clock phase
• Choice of 8/16/24/32-bit width of transmit/receive data
• Full-duplex communication capability
• Consecutive serial communication
• Choice of LSB-first or MSB-first transfer
• Choice of a clock source
• Five interrupt sources
• Module stop state can be set.
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Section 20 Synchronous Serial Communication Unit (SSU)
The shift register is incorporated, enabling transmission and reception to be executed
simultaneously.
Seven internal clocks (φ/4, φ/8, φ/16, φ/32, φ/64, φ/128, φ/256) or an external clock
Transmit-end, transmit-data-register-empty, receive-data-full, overrun-error, and conflict error
Features
Section 20 Synchronous Serial Communication Unit (SSU)
Page 1099 of 1392

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