R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 843

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2456, H8S/2456R, H8S/2454 Group
12.4.4
During non-overlapping operation, transfer from NDR to PODR is performed as follows:
•
•
Figure 12.6 illustrates the non-overlapping pulse output operation.
Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before
compare match A.
The NDR contents should not be altered during the interval from compare match B to compare
match A (the non-overlap margin).
This can be accomplished by having the TGIA interrupt handling routine write the next data in
NDR, or by having the TGIA interrupt activate the DTC or DMAC. Note, however, that the next
data must be written before the next compare match B occurs.
Figure 12.7 shows the timing of this operation.
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
if their value is 1.
NDR bits are always transferred to PODR bits at compare match A.
At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred
Pulse
output
pin
Non-Overlapping Pulse Output
DDR
Figure 12.6 Non-Overlapping Pulse Output
Normal output/inverted output
Q
NDER
Q
PODR
C
D
Section 12 Programmable Pulse Generator (PPG)
Q
NDR
Compare match A
Compare match B
D
Internal data bus
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