R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 521

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2456, H8S/2456R, H8S/2454 Group
Section 9 Data Transfer Controller (DTC)
9.5
Operation
The DTC stores register information in the on-chip RAM. When activated, the DTC reads register
information that is already stored in the on-chip RAM and transfers data on the basis of that
register information. After the data transfer, it writes updated register information back to the on-
chip RAM. Pre-storage of register information in the on-chip RAM makes it possible to transfer
data over any required number of channels. There are three transfer modes: normal mode, repeat
mode, and block transfer mode. Setting the CHNE bit to 1 makes it possible to perform a number
of transfers with a single activation (chain transfer). A setting can also be made to have chain
transfer performed only when the transfer counter value is 0. This enables DTC re-setting to be
performed by the DTC itself.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed.
Figure 9.5 shows a flowchart of DTC operation, and table 9.3 summarizes the chain transfer
conditions (combinations for performing the second and third transfers are omitted).
REJ09B0467-0350 Rev. 3.50
Page 491 of 1392
Jul 07, 2010