R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 648
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 10 I/O Ports
10.10
Port B is an 8-bit I/O port that also has other functions. Port B has the following registers.
• Port B data direction register (PBDDR)
• Port B data register (PBDR)
• Port B register (PORTB)
• Port B pull-up MOS control register (PBPCR)
• Port B open drain control register (PBODR)
10.10.1 Port B Data Direction Register (PBDDR)
The individual bits of PBDDR specify input or output for the pins of port B. PBDDR cannot be
read; if it is, an undefined value will be read.
Page 618 of 1392
Bit
7
6
5
4
3
2
1
0
Bit Name
PB7DDR
PB6DDR
PB5DDR
PB4DDR
PB3DDR
PB2DDR
PB1DDR
PB0DDR
Port B
Initial Value
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
Description
•
•
•
Modes 1 and 2
Port B pins are address outputs regardless of the
PBDDR settings.
Modes 7 (when EXPE = 1) and 4
Setting a PBDDR bit to 1 makes the
corresponding pin an address output, while
clearing a PBDDR bit to 0 makes the
corresponding pin an input port.
Mode 7 (when EXPE = 0)
Port B is an I/O port, and its pin functions can be
switched with PBDDR.
H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
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