R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 382

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2456, H8S/2456R, H8S/2454 Group
Section 7 DMA Controller (DMAC)
7.4.1
Activation by Internal Interrupt Request
An interrupt request selected as a DMAC activation source can also simultaneously generate an
interrupt request for the CPU or DTC. For details, see section 5, Interrupt Controller.
With activation by an internal interrupt request, the DMAC accepts the interrupt request
independently of the interrupt controller. Consequently, interrupt controller priority settings are
irrelevant.
If the DMAC is activated by a CPU interrupt source or an interrupt request that is not used as a
DTC activation source (DTA = 1), the interrupt request flag is cleared automatically by the DMA
transfer. With ADI, TXI, and RXI interrupts, however, the interrupt source flag is not cleared
unless the relevant register is accessed in a DMA transfer. If the same interrupt is used as an
activation source for more than one channel, the interrupt request flag is cleared when the highest-
priority channel is activated. Transfer requests for other channels are held pending in the DMAC,
and activation is carried out in order of priority.
When DTE = 0 after completion of a transfer, an interrupt request from the selected activation
source is not sent to the DMAC, regardless of the DTA bit setting. In this case, the relevant
interrupt request is sent to the CPU or DTC.
When an interrupt request signal for DMAC activation is also used for an interrupt request to the
CPU or DTC activation (DTA = 0), the interrupt request flag is not cleared by the DMAC.
If the DMAC is activated by a USB interrupt source, setting bits DTF[3:0] in DMACR to 4'b0011
and the USBDRQE bit in PFCR3 to 1 activates the DMAC at a low-level input of the USB
interrupt signal.
The DMAC stands by for a transfer request while the USB interrupt source is held high. While the
USB interrupt source is held low, transfers continue in succession, with the bus being released
each time a byte or word is transferred. If the USB interrupt source goes high in the middle of a
transfer, the transfer is interrupted and the DMAC stands by for a transfer request.
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REJ09B0467-0350 Rev. 3.50
Jul 07, 2010