R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 433

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2456, H8S/2456R, H8S/2454 Group
• If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC
(2)
When the MSTP13 bit in MSTPCRH is set to 1, the DMAC clock stops, and the module stop state
is entered. However, 1 cannot be written to the MSTP13 bit if any of the DMAC channels is
enabled. This setting should therefore be made when DMAC operation is stopped.
When the DMAC clock stops, DMAC register accesses can no longer be made. Since the
following DMAC register settings are valid even in the module stop state, they should be
invalidated, if necessary, before a module stop.
•
•
•
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
register is read as shown in figure 7.40.
Transfer end/break interrupt (DTE = 0 and DTIE = 1)
TEND pin enable (TEE = 1)
DACK pin enable (FAE = 0 and SAE = 1)
Module Stop
φ
DMA internal
address
DMA register
operation
DMA control
Figure 7.40 Contention between DMAC Register Update and CPU Read
Note: The lower word of MAR is the updated value after the operation in [1].
MAR upper
word read
Idle
CPU longword read
[1]
MAR lower
word read
Transfe
source
Read
[2]
DMA read
destination
DMA transfer cycle
Transfer
Write
DMA write
Section 7 DMA Controller (DMAC)
Idle
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