R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 1186

MCU 128KKB FLASH 48K 144-LQFP

R4F24568NVFQV

Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheets

Specifications of R4F24568NVFQV

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R4F24568NVFQV
Manufacturer:
REA
Quantity:
15
Part Number:
R4F24568NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
H8S/2456, H8S/2456R, H8S/2454 Group
Section 22 Flash Memory
22.4.5
Block Erase
Write H'20xx in the first bus cycle and H'D0xx to the lowest address (an even address) of the
target block in the second cycle; automatic erasure (erasing data and verifying the erased status)
starts in the specified block.
Completion of automatic erasure can be checked through the FMRDY bit in FLMSTR.
The FMRDY bit is 0 (busy) during automatic erasure and becomes 1 (ready) when erasure is
completed.
After automatic erasure is completed, the result can be checked through the FMERSF bit in
FLMSTR (see section 22.6, Full Status Check).
Figure 22.4 shows a flowchart of the block erase command processing.
In the EW0 mode, the read status register mode is entered as soon as automatic erasure starts, and
the status register can be read. The SR7 bit in the status register becomes 0 when automatic
erasure starts and returns to 1 when erasure is completed. In this case, the flash memory stays in
the read status register mode until a read array command is issued. If an erase error occurs, repeat
a sequence of the clear status register command to block erase command at least three times until
no erase error occurs.
Page 1156 of 1392
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010

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