R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 1005

MCU 128KKB FLASH 48K 144-LQFP

R4F24568NVFQV

Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheets

Specifications of R4F24568NVFQV

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R4F24568NVFQV
Manufacturer:
REA
Quantity:
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Part Number:
R4F24568NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Bit
1
Bit Name
EP2 DMAE
Initial
Value
0
R/W
R/W
Description
EP2 DMA Transfer Enable
When this bit is set, DMA transfer is enabled from
memory to the endpoint 2 transmit FIFO buffer. If
there is at least one byte of open space in the FIFO
buffer, a DMA transfer request signal (USB INTN1) is
asserted. In DMA transfer, when 64 bytes are written
to the FIFO buffer the EP2 packet enable bit is set
automatically, allowing 64 bytes of data to be
transferred, and if there is still space in the other side
of the two FIFOs, the DMA transfer request signal
(USB INTN1) is asserted again. However, if the size
of the data packet to be transmitted is less than 64
bytes, the EP2 packet enable bit is not set
automatically, and so should be set by the CPU with a
DMA transfer end interrupt.
As EP2-related interrupt requests to the CPU are not
automatically masked, interrupt requests should be
masked as necessary in the interrupt enable register.
1. Write of 1 to the EP2 DMAE bit in DMAR
2. Set the DMAC to activate through DREQ1
3. Transfer count setting in the DMAC
4. DMAC activation
5. DMA transfer
6. DMA transfer end interrupt generated
See section 16.8.4, DMA Transfer for Endpoints 2.
Operating procedure
(USB INTN1)
Section 16 USB Function Module (USB)
Page 975 of 1392

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